From a theoretical viewpoint, an FSK-type signal S(t) received by the antenna of a detection circuit can be shown, on two axes I0, Q0 in quadrature, by a rotating vector having an abscissa IL0(t) and an ordinate QL0(t) (see FIG. 1). The direction of rotation of the vector corresponds to the binary data contained in the signals IL0 (t), QL0 (t). Thus, when the direction of rotation of the vector is positive (clockwise direction of rotation), the binary data represented by the vector is a logical “1”; conversely, when the direction of rotation of the vector is negative, then the binary data is a logical “0”. On the other hand, the speed of rotation of the vector corresponds to the value of the frequency departure of the modulated signal in relation to the carrier signal and is therefore dependent on the modulation frequency of the carrier (in the example, the frequency departure is +2 MHz when a logical “1” is transmitted and −2 MHz when a logical “0” is transmitted). The relationship between the frequency departure and the data transmission frequency is called the modulation index, this index corresponds to the number of revolutions completed by the rotating vector as one bit of data is transmitted. For example, if the modulation frequency of the carrier is 2 MHz and the data transmission frequency is 1 MHz, then, as one bit of data is transmitted, the vector completes two revolutions (modulation index =2) and thereby intersects the axes IL0 or QL0 an average of 8 times. On this subject, see, in particular, document D1: “A Novel Digital FM Receiver for Mobile and Personal Communications,” IEEE Transactions on Communications, Vol. 44, No. 11, Nov. 1996, pp. 1466-1476.
The direction of rotation of the vector at a given moment t is dependent, in particular, on the mathematical derivatives of the signals IL0(t), QL0(t) at the moment t in question. A simple way of determining the direction of rotation of the rotating vector is to observe the derivative of QL0(t) at the moment when IL0(t) passes through +/−1 (i.e., when the rotating vector intersects the axis I0), or conversely, to observe the derivative of IL0(t) at the moment when QL0(t) passes through +/−1 (i.e., when the rotating vector intersects the axis Q0). In other words, on the one hand, the zero crossing of one of the signals IL0(t), QL0(t) is determined (when the other signal is equal to +/−1) and, on the other hand, the zero crossing order of the signals IL0(t), QL0(t).
In order to obtain more accurate results, several pairs of supplementary axes (I1, Q1), (I2, Q2), ..., (IM, QM) are used (see FIG. 1). Each pair of supplementary axes is derived from the initial pair of axes (I0, Q0) by an increasing or decreasing phase shift with respect to M, ranging, for example, between 0 and Π/2; in this case, and in a similar way in the case where a single pair of axes is used, the ZCD demodulator scans the rotating vector, determines the moment when the vector intersects one of the axes I0, I1, . . ., IM, Q1, Q2, . . ., QM, determines the crossing order of the various axes and deduces therefrom the value of the transmitted data.
FIG. 2 shows a block diagram of an FSK signal detection circuit comprising an antenna 10, an axes generator 20 and a ZCD demodulator. The detection circuit receives the modulated signal S(t) on the antenna 10 and extracts from it the binary data DATA that it contains.
The axes generator 20 produces two signals IL0(t), QL0(t) from the modulated signal S(t) that it receives on the antenna 10. To accomplish this, the axis generator filters the signal S(t) and amplifies it through the filter 22 and the amplifier 24. In parallel, a generator 32 of the PLL type (Phase Lock Loop) produces a reference frequency signal equal to the carrier frequency of the modulated signal S(t) received on the antenna (in a 2.45 GHz example); the reference signal is phase-shifted by Π/2 in a phase shifter 34. In a first branch, the amplified signal SA(t) (with a frequency of 2.45 GHz +/−2 MHz) is multiplied by the reference signal (multiplier 42); the multiplication result is filtered by the filter 44 to delete the 2*2.45 GHZ +/−2 MHz frequency component and to retain only the 2 MHz frequency component corresponding to the binary data. This latter component is then clipped (i.e., limited in amplitude by a clipper 46) in order to produce a signal IL0(t) having an amplitude ranging between 0 and 1. In a second branch, the amplified signal SA(t) (having a frequency of 2.45 GHz +/−2 MHz) is multiplied (multiplier 52) by the reference signal phase-shifted by Π/2, filtered by a filter 54 (deletion of the component of the 2*2.45 GHZ +/−2 MHz frequency signal), then clipped (clipper 56) in order to produce a signal QL0(t) having an amplitude ranging between 0 and 1. For all practical purposes, the signal QL0(t) is the signal IL0(t) produced by the first branch, phase-shifted by Π/2 The signals IL0(t), QL0(t) contain only the 2 MHz frequency binary data initially contained in the modulated signal S(t), the carrier signal having been eliminated by the filters 44, 54.
The axes generator also produces M pairs of supplementary signals (IL1(t), QL1(t), . . ., (ILM(t), QLM(t)) and converts them into corresponding binary signals (IL1, QL1), . . ., (ILM, QLM). Thus, for any i:ILi=0 if ILi(t)<0ILi=1 if ILi(t)>0QLi=0 if QLi(t)<0QLi=1 if QLi(t)>0
The signals (IL1(t), QL1(t), . . ., (ILM(t), QLM(t)), and therefore also the corresponding binary signals (IL1, QL1), . . ., (ILM, QLM) are all derived from the signals (IL0(t), QL0(t)) by an increasing or decreasing phase shift with respect to M, M being a fixed integer.
The signals (IL1, QL1), . . ., (ILM, QLM) are next supplied to a ZCD demodulator 60 that will extract from them the binary data DATA that they contain. In order to accomplish this, the ZCD demodulator includes a set of zero-crossing detectors DPZO1, DPZ02, . . ., DPZOM.
According to a known structure, the ZCD demodulator is of the synchronous type.
Each DPZOi detector of digit position i falling between 1 and M receives a pair of signals (ILi, QLi) of the same digit position and produces a pulse DEi at each rising edge of an external clock CLK such that:
DEi=1 if                ILi=1 when QLi passes from 0 to 1, or        QLi=1 when ILi passes from 1 to 0        
DEi=0 if                ILi=1 when QLi passes from 1 to 0, or        
QLi=1 when ILi passes from 0 to 1
The pulses DE1, DE2, . . ., DEM are used to increment or decrement a digital counter that is synchronized by the clock signal CLK. At each rising edge of the clock signal CLK:
if one of the pulses DEi=1, the counter is incremented,
if one of the pulses DEi=0, the counter is decremented.
Then, at each pulse of an RST signal, the counter produces a piece of binary data that is:                D=1 if the value of the counter is positive,        D=0 if the value of the counter is negative, then the counter is reset to zero.        
The counter thus serves as an integrator which integrates the signal resulting from the sum of the pulses DE1, DE2, . . ., DEM over a time period equal to the period of the RST signal.
This structure requires that there be a clock signal generator, in addition to the ZCD decoder, and preferably a good quality generator.
The applicant has proposed a solution to these disadvantages in the application FR-04 10324, unpublished as of the date of filing of this application. This document describes an asynchronous ZCD demodulator. This demodulator, shown in FIG. 3, includes a decoder that produces binary data DATA when it receives a set of pairs of logic signals (IL1, QL1), . . ., (ILM, QLM) and extracts from them the digital data DATA that they contain. Each pair of logic signals (ILi, QLi) corresponds to the binary value of the pair of signals (ILi(t), QLi(t)). The ZCD decoder includes a set of zero-crossing detectors DPZ1, DPZ2, . . ., DPZM, and an asynchronous envelope detector 150.
The zero-crossing detectors (DPZ1, . . . , DPZM), are asynchronous logic circuits generating pulses with respect to logic signals (ILi, QLi).                Pulses Pi are generated when:                    ILi=1 when QLi passes from 0 to 1, or            QLi=1 when ILi passes from 1 to 0                        Pulses Ni are generated when:                    ILi=1 when QLi passes from 1 to 0, or            QLi=1 when ILi passes from 0 to 1                        
The pulses Ni are applied to a first OR gate to form a signal N. The pulses Pi are applied to a second OR gate to form a signal P. The asynchronous envelope detector produces the binary data DATA after having generated an envelope from the pulses Pi and Ni.
The timing chart of FIG. 4 shows the possible impact of interference on the output signal of the decoder of FIG. 3. The interference may lead to unwanted crossings of the axes by the logic signals ILi and QLi. These unwanted crossings lead to spurious pulses P and N circled in FIG. 4. Thus, some pulses P are replaced by pulses N and vice versa. The binary signal Data coming from the envelope detector is then corrupted in relation to the original binary signal D-E. Determination of the symbol received is then corrupted.